For Memory Validations, I use Samsung based Chipsets and run around 1.8 to 1.9v. The best spot for DRAM Voltage obviously depends on the ICs used. VTT is best left at half of DRAM voltage. After that, 1.18v VCCIO and 1.25v SA can get you close to 3800, and then 1.25v VCCIO with 1.3v VCCSA will get you to v VCCIO may get you further, I have not found higher than 1.3v to help scale further. 1.12v on VCCIO and 1.12v on VCCSA is enough for up to around 3500 in Frequency, depending on configurations.
VCCIO has a relationship with DMI voltage so I would just leave DMI voltage at auto when I change VCCIO to let the BIOS determine the best spot for DMI voltage. The 2 rails that affect DRAM overclocking are VCCIO and VCCSA. First off, there are a lot more ratios you can use this time, the even ratios you are used to and the odd ratios that are new. Always load defaults save exit once after a cleared cmos before changing bclk.ģ DRAM You can use our Memory Presets as start off points: One of the most significant improvements you will see on Skylake is the Memory Frequency overclocking and granularity. Level 6 PLL Bandwidth + 1.7v PLL Termination v PCH + Lowest CPU Ratio + Lowest Dram Ratio + Lowest Cache Ratio should get you around 400BCLK on air. Remember to set Core Ratio and Ring Ratio to 8x, and Memory Ratio to the lowest when pushing BCLK. Also remember to raise PCH Core voltage to 1.1v~1.2v, if not it will 00 at reset. When you set higher than 1.45v on PLL Termination, remember to raise CPU Standby. Easiest would be to synchronize these 2 rails.
When using 1.50v PLL Termination you will probably want at least around 1.20v on CPU Standby Voltage. Now try to keep a less than 450mv delta between PLL Termination voltage and CPU Standby Voltage. You should gain some more with 1.50v++ PLL Termination. 1.45v PLL Termination with Level 6 on PLL Bandwidth should give you very good margins, while raising both of these may help some more when you have good cooling. Just concern yourself with these 2 rails: (For those ROG boards such as M8H without PLL Termination voltage, use CPU standby Voltage instead as it is shared with PLL Termination on this board) Having a rightly matched set of the above two options will improve your base clock margin. Just key in the Base Clock you want and don t need to worry about the weak DMI bus as it always stays at default. Now you don t have to be bothered by the Base Clock Straps you had to deal with in the past. 26Ģ #You can use our Overclocking Presets as start off points: I ll separate the OC Guide into the various domains as usual: BCLK Skylake features a really high Base Clock headroom for the K processors.
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